In recent years, interest has developed concerning FETs which include a so-called "floating gate" in a stacked arrangement with the control gate. The floating gate differs from a control gate in that it is not electrically connected to any external component and is surrounded by isolation on all sides. Examples of some disclosures of such FETs include U.S. Pat. No. 3,825,945 to Masuoka, U.S. Pat. No. 3,825,946 to Frohman-Bentchkowsky, U.S. Pat. No. 3,836,992 to Abbas et al, U.S. Pat. No. 3,868,187 to Masuoka, U.S. Pat. No. 3,881,180 to Gosney, Jr., U.S. Pat. No. 3,893,151 to Bosselaar et al, U.S. Pat. No. 3,950,738 to Hayashi et al, U.S. Pat. No. 3,984,822 to Simko et al, and U.S. Pat. No. 3,985,591 to Arita.
The presence of the control gate enables the device to function as a regular IGFET, while the floating gate provides a storage space for injected electrons or holes, and thus enables the device to function as an electrically reprogrammable memory device. The floating gate provides a method for changing the threshold voltage needed to pass a charge from the source to the drain. The presence of the control over the floating gate adds control to the injection of charges into the floating gate.
The processes previously suggested for fabricating FETs having a stacked arrangement of a floating gate and a control gate including the patents referred to hereinabove involve the use of at least one additional lithographic masking operation as compared to methods for providing FETs with only one of the gates. The lithographic masking steps involved in preparing integrated circuits are among the most critical. The lithographic masking steps require high precision in registration and extreme care in execution. Each additional lithographic masking step in a process introduces possible surface damage due to mask defects, and increases mask-to-mask registration problems that decrease the processing yield and, accordingly, significantly increase the fabrication cost. Although other factors affect the yield and cost such as, for example, the number of high temperature heat treatments, a basic objective in all FET integrated circuit fabrication is to minimize the number of basic lithographic masking steps required to produce a particular integrated circuit array of desired device structures.
Accordingly, an object of the present invention is to provide a fabrication process for producing integrated circuits of FETs which requires a minimum number of masking steps.
The fabrication of source and drain self-aligned with respect to an FET gate, particularly a polysilicon gate, is well known. In the self-aligned gate technique, a gate (e.g., polysilicon gate) is delineated prior to forming the source and drain regions. The edges of the gate material and the edges of the field isolation serve as a mask for defining the boundaries of the diffused or ion implanted source and drain regions. A method of fabrication for ion implanted self-aligned source and drain regions is described in "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions" by R. H. Dennard et al, IEEE J. Solid-State Circuits, Vol. SC-9, pp. 256-268 (October 1974). Other disclosures of interest relative to self-aligned techniques include U.S. Pat. No. 3,849,216 to Salters, U.S. Pat. No. 3,895,390 to Meiling et al, U.S. Pat. No. 3,897,282 to White, U.S. Pat. No. 3,946,419 to DeWitt et al, U.S. Pat. No. 3,967,981 to Yamazaki, and U.S. Pat. No. 3,972,756 to Nagase et al. U.S. Pat. No. 3,996,657 to Simko et al suggests a stacked polysilicon gate arrangement wherein a secondary source and drain regions are self-aligned with a floating gate prior to formation of a control gate and formation of primary source and drain regions in alignment with the control gate. U.S. Pat. No. 3,897,282 to White as well as U.S. Pat. No. 3,984,822 to Simko et al suggest stacked polysilicon gate arrangements wherein only the gate closest the semiconductive substrate is self-aligned with the source and drain regions.
Moreover, the article in May, 1977 in IEEE Transactions on Electron Devices, Volume ED-24, No. 5, by A. Scheibe et al entitled "Technology of a New n-Channel One-Transistor EAROM Cell Called SIMOS" seems to suggest a process whereby the control gate and floating gate are self-aligned in the width direction but not in the length direction. The control gate is longer than the floating gate, and therefore, the control gate and floating gate are not completely self-aligned.
The process suggested in this article involves a first masking step to "provisionally" define the floating gate after which an oxide and polysilicon material are deposited. Then a second masking procedure is carried out which defines the control gate and also removes any portions of the floating gate that may exceed the control gate. Next, the source and drain region are formed. The source and drain are self-aligned along the length of the control gate bounded by the field isolation edges. As shown in FIG. 2 of said article, the length dimension of the control gate is longer than the length dimension of the floating gate. In addition to requiring additional masking operations, the process suggested in said article also requires an additional step after the floating gate is provisionally defined to provide insulation of the edges of the floating gate which would have been exposed in the delineation process.
According to the present invention, both the width and length dimensions of the floating gate and control gate are self-aligned with each other and self-aligned with the source and drain regions. The self-alignment according to the present invention is achieved with a minimum number of masking steps. Along with the self-alignment, since the lateral dimensions of the gates are the same, the area occupied by the gates in minimized. This in turn results in reduced overlap capacitance.